CSE240A Stride and Sequential Prefetcher

Since processor becomes faster and faster and memory system improves less, the access time of memory system becomes significantly important. To narrow the gap between processor and memory system, a more clever way of utilizing cache are needed. In this project, I’m trying to design a small device and algorithm to prefetch blocks from lower level memory to L1 D-cache efficiently and correctly. This is component is one of the most important factors to speed up memory system. Because the next line cache prefetch mechanism can not often match the pattern of program, we need some instruction predicted method to guess which block of memory are going to be needed in the future. In this project, I combined and modified two basic prefetch designs. The first one is stream buffer from [1] and the second one is the stride prefetcher from [2]. The reason of combining these two designs is that they can conquer different kind of patterns separately. In a high spatial locality environment, stream buffer performs very well. For stride prefetcher, it can predict iterative pattern excellently. Combining these two designs can make my prefetcher become more powerful.